The M-sequence generator of claim 1, wherein: said linear feedback shift register is an N-bit linear feedback shift register, N being a positive integer said shifted state data comprise N bits the mask data stored in said mask table comprise N×N bits for each of said different phase shifts and said masked operation circuit obtains each bit of said shifted state data by masking the data read from said linear feedback shift register according to N bits of said mask data to obtain masked data, and performing a logical operation on the masked data.ģ. An M-sequence generator having a linear feedback shift register that generates an M-sequence, also comprising: a mask table storing mask data corresponding to at least two different phase shifts of the M-sequence a masked operation circuit coupled to said mask table, performing logic operations on data read in parallel from said linear feedback shift register and mask data read from said mask table, thereby obtaining shifted state data and a control unit coupled to said mask table, selecting the mask data supplied to said masked operation circuit, loading the shifted state data from said masked operation circuit into said linear feedback shift register, and repeating these operations, selecting different mask data in said mask table, to obtain an arbitrary total phase shift in said M-sequence.Ģ.
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